Typical Applications (continued)
9.2.3 MPPT Disabled, Low Impedance Source Application Circuit
SLUSAH0C – OCTOBER 2011 – REVISED JUNE 2015
Primary Battery or
other Low Z source
L BST CBYP (1)
16 15 ` 14
4 VREF _SAMP
OT_PROG VBAT_OV VRDIV VBAT_UV
(1) Place close as possible to IC pin 15 (VSTOR) and pin 13 (VSS)
(2) See the Capacitor Selection section for guidance on sizing CSTOR
Figure 28. Typical MPPT Disabled Application Circuit
(Low Iq Boost Converter from Low Impedance Source)
184.108.40.206 Design Requirements
The input source is a low impedance 1.2 V battery therefore MPPT is not needed. The output will be a low ESR
capacitor therefore VSTOR can be tied to VBAT and VBAT_UV is not needed. The desired voltage levels are
VBAT_OV = 3.30 V, VBAT_OK = 2.80 V, VBAT_OK_HYST = 3.10 V, and MPPT disabled. The IC must stop
charging if its junction temperature is above 65°C. Load transients are expected.
220.127.116.11 Detailed Design Procedure
The recommended L1 = 22 µH, CBYP = 0.01 µF and low leakage CREF = 10 nF are selected. The minimum
recommended CIN = 4.7 µF is selected. To prevent VSTOR from drooping during system load transients,
CSTOR is set to 100 µF. To disable the sampling for MPPT, the VOC_SAMP pin is tied to VSTOR. To disable
the input voltage regulation circuit, the VREF_SAMP pin is tied to GND. Since the VBAT_UV function is not
needed, the VBAT_UV can be tied to VSTOR. To stop charging when the IC junction temperature is above 65°C,
the OT_PROG pin is tied to GND.
Referring back to the procedure in Detailed Design Procedure or using the spreadsheet calculator at SLURAQ1
gives the following values:
• ROV1 = 5.62 MΩ, ROV2 = 4.22 MΩ resulting in VBAT_OV = 3.28 V due to rounding to the nearest 1% resistor.
• ROK1 = 4.12 MΩ, ROK2 = 5.11 MΩ, ROK3 = 0.976 MΩ resulting in VBAT_OK = 2.80 V and VBAT_OK_HYST =
3.10 V after rounding.
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