Typical Applications (continued)
9.2.2 TEG Application Circuit
SLUSAH0C – OCTOBER 2011 – REVISED JUNE 2015
16 15 ` 14
4 VREF _SAMP
OT_PROG VBAT_OV VRDIV VBAT_UV
(1) Place close as possible to IC pin 15 (VSTOR) and pin 13 (VSS)
(2) See the Capacitor Selection section for guidance on sizing CSTOR
Figure 21. Typical TEG Application Circuit
126.96.36.199 Design Requirements
The desired voltage levels are VBAT_OV = 4.25 V, VBAT_UV = 3.20 V, VBAT_OK = 3.55 V, VBAT_OK_HYST =
3.76 V and MPP (VOC) = 50% which is typical for TEG harvesters. The IC must stop charging if its junction
temperature is above 120°C. The simulated TEG open circuit voltage is 1.0 V.
188.8.131.52 Detailed Design Procedure
The recommended L1 = 22 µH, CBYP = 0.01 µF and low leakage CREF = 10 nF are selected. In order to ensure
the fastest recovery of the harvester output voltage to the MPPT level following power extraction, the minimum
recommended CIN = 4.7 µF is selected. Because no large system load transients are expected and to ensure
fast charge time during cold start, the minimum recommended CSTOR = 4.7 µF. To stop charging when the IC
junction temperature is above 120°C, the OT_PROG pin is tied to VSTOR.
Referring back to the procedure in Detailed Design Procedure or using the spreadsheet calculator at SLURAQ1
gives the following values:
• ROV1 = 4.42 MΩ, ROV2 = 5.49 MΩ resulting in VBAT_OV = 4.26 V due to rounding to the nearest 1% resistor.
• RUV1 = 3.83 MΩ, RUV2 = 6.04 MΩ resulting in VBAT_UV = 3.22 V due to rounding to the nearest 1% resistor
• ROK1 = 3.32 MΩ, ROK2 = 6.04 MΩ, ROK3 = 0.536 MΩ resulting in VBAT_OK = 3.52 V and
VBAT_OK_HYST = 3.73 V after rounding.
• ROC1 = 10 MΩ and ROC2 = 10 MΩ gives 50% MPP voltage.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq25504
Submit Documentation Feedback