Accelerator Series FPGAs – ACT™ 3 Family
A1440A, A14V40A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)1
Logic Module Propagation Delays2
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed
‘Std’ Speed 3.3V Speed1
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
Internal Array Module
tCO
Sequential Clock to Q
tCLR
Asynchronous Clear to Q
Predicted Routing Delays3
2.0
2.3
2.6
3.0
3.9 ns
2.0
2.3
2.6
3.0
3.9 ns
2.0
2.3
2.6
3.0
3.9 ns
tRD1
FO=1 Routing Delay
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
Logic Module Sequential Timing
0.9
1.0
1.1
1.3
1.7 ns
1.2
1.4
1.6
1.8
2.4 ns
1.4
1.6
1.8
2.1
2.8 ns
1.7
1.9
2.2
2.5
3.3 ns
2.8
3.2
3.6
4.2
5.5 ns
tSUD
Flip-Flop Data Input Setup 0.5
0.6
0.7
0.8
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUD
Latch Data Input Setup
0.5
0.6
0.7
0.8
0.8
ns
tHD
Latch Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width 1.9
2.4
3.2
3.8
4.8
ns
tWCLKA
Flip-Flop Clock Pulse Width 1.9
2.4
3.2
3.8
4.8
ns
tA
Flip-Flop Clock Input Period 4.0
5.0
6.8
8.0
10.0
ns
fMAX
Flip-Flop Clock Frequency
250
200
150
125
100 MHz
Notes:
1. VCC = 3.0 V for 3.3V specifications.
2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
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