A14100 View Datasheet(PDF) - Microsemi Corporation
Part Name
Description
Manufacturer
A14100 Datasheet PDF : 90 Pages
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Detailed Specifications
A1460A, A14V60A Timing Characteristics
Table 2-30 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1
Logic Module Propagation Delays2 –3 Speed3 –2 Speed 3 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPD Internal Array Module
tCO Sequential Clock to Q
tCLR Asynchronous Clear to Q
Predicted Routing Delays4
2.0
2.3
2.6
3.0
3.9 ns
2.0
2.3
2.6
3.0
3.9 ns
2.0
2.3
2.6
3.0
3.9 ns
tRD1 FO = 1 Routing Delay
tRD2 FO = 2 Routing Delay
tRD3 FO = 3 Routing Delay
tRD4 FO = 4 Routing Delay
tRD8 FO = 8 Routing Delay
Logic Module Sequential Timing
0.9
1.0
1.1
1.3
1.7 ns
1.2
1.4
1.6
1.8
2.4 ns
1.4
1.6
1.8
2.1
2.8 ns
1.7
1.9
2.2
2.5
3.3 ns
2.8
3.2
3.6
4.2
5.5 ns
tSUD Flip-Flop Data Input Setup
0.5
0.6
0.7
0.8
0.8
ns
tHD Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUD Latch Data Input Setup
0.5
0.6
0.7
0.8
0.8
ns
tHD Latch Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tWASYN Asynchronous Pulse Width 2.4
3.2
3.8
4.8
6.5
ns
tWCLKA Flip-Flop Clock Pulse Width 2.4
3.2
3.8
4.8
6.5
ns
tA
Flip-Flop Clock Input Period 5.0
6.8
8.0
10.0
13.4
ns
fMAX Flip-Flop Clock Frequency
200
150
125
100
75 MHz
Notes:
1. VCC = 3.0 V for 3.3 V specifications.
2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
2-34
Revision 3
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