Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol
SFDR
Description
Spurious free
dynamic range
Conditions
• Gain=1
• Gain=64
ENOB Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
Min.
85
53
11.6
8.0
7.2
6.3
12.8
11.0
7.9
7.3
6.8
6.8
7.5
Typ.1
105
88
Max.
—
—
13.4
—
13.6
—
9.6
—
9.6
—
14.5
—
14.3
—
13.8
—
13.1
—
12.5
—
11.5
—
10.6
—
Unit
Notes
dB
16-bit
dB
differential
mode,
Average=32,
fin=100Hz
bits
16-bit
bits
differential
mode,fin=100Hz
bits
bits
bits
bits
bits
bits
bits
bits
bits
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
IDDHS Supply current, High-speed mode (EN=1, PMODE=1)
—
—
IDDLS Supply current, low-speed mode (EN=1, PMODE=0)
—
—
VAIN
Analog input voltage
VSS – 0.3
—
VAIO
Analog input offset voltage
—
—
3.6
V
200
μA
20
μA
VDD
V
20
mV
Table continues on the next page...
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.
45