K10P81M100SF2V2 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

K10P81M100SF2V2

K10 Sub-Family

NXP Semiconductors. 

General

Table 9. Device clock specifications (continued)

Symbol Description

fLPTMR_ERCLK

fFlexCAN_ERCLK

fI2S_MCLK

fI2S_BCLK

LPTMR external reference clock

FlexCAN external reference clock

I2S master clock

I2S bit clock

Min.

—

—

—

—

Max.

16

8

12.5

4

Unit

MHz

MHz

MHz

MHz

Notes

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

5.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

CAN, CMT, and I2C signals.

Table 10. General switching specifications

Symbol

Description

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

Mode select (EZP_CS) hold time after reset

deassertion

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

Port rise and fall time (low drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

Min.

1.5

100

16

100

2

—

—

—

—

—

—

—

—

Max.

—

—

—

—

—

Unit

Bus clock

cycles

ns

ns

ns

Bus clock

cycles

Notes

1, 2

3

3

3

4

12

ns

6

ns

36

ns

24

ns

5

12

ns

6

ns

36

ns

24

ns

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

20

Freescale Semiconductor, Inc.

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