K10P81M100SF2V2 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

K10P81M100SF2V2

K10 Sub-Family

NXP Semiconductors. 

Table 5. Power mode transition operating behaviors

Symbol

tPOR

Description

After a POR event, amount of time from the point VDD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

• VDD slew rate ≥ 5.7 kV/s

• VDD slew rate < 5.7 kV/s

• VLLS1 → RUN

Min.

Max.

Unit

—

300

μs

—

1.7 V / (VDD

slew rate)

—

130

μs

• VLLS2 → RUN

—

92

μs

• VLLS3 → RUN

—

92

μs

• LLS → RUN

—

5.9

μs

• VLPS → RUN

—

5.0

μs

• STOP → RUN

—

5.0

μs

1. Normal boot (FTFL_OPT[LPBOOT]=1)

General

Notes

1

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

Symbol

IDDA

IDD_RUN

Description

Analog supply current

Run mode current — all peripheral clocks

disabled, code executing from flash

• @ 1.8V

• @ 3.0V

Min.

—

—

—

Typ.

Max.

Unit

—

See note

mA

37

63

mA

38

64

mA

IDD_RUN

Run mode current — all peripheral clocks

enabled, code executing from flash

• @ 1.8V

• @ 3.0V

• @ 25°C

• @ 125°C

—

46

77

mA

—

47

63

mA

—

58

79

mA

IDD_WAIT Wait mode high frequency current at 3.0 V — all

—

20

—

mA

peripheral clocks disabled

IDD_WAIT Wait mode reduced frequency current at 3.0 V —

—

9

—

mA

all peripheral clocks disabled

IDD_VLPR Very-low-power run mode current at 3.0 V — all

—

1.12

—

mA

peripheral clocks disabled

Table continues on the next page...

Freescale Semiconductor, Inc.

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

Notes

1

2

3, 4

2

5

6

15

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