AR9271 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

AR9271

Single-Chip 1x1 MAC/BB/Radio/PA/LNA with USB Interface for 802.11n 2.4 GHz WLANs

Unspecified 

18

17

16:15

14

13

12

11

10

9

8

7

6

MAIN_PLL_ R/W

PWD_CTL

CLKIN_CTL R/W

RES

GATE_MAC_

CTL

R

R/W

USB_RST_SEL R/W

USB_POR

R/W

USB_SUSPEND R/W

BB_WARM_RST R/W

BB_COLD_RST R/W

CG_COLD_RST R/W

RADIO_WARM R/W

_RST

RADIO_COLD_ R/W

RST

0x0 Sets the type of mechanism to be used to power down the main

PLL

0 Allows the USB suspend mechanism to control the power

down of the main PLL

1 Power down the main PLL

0x0 Sets the type of gate 40 MHz clock

0 Allows the USB suspend mechanism control the gate 40

MHz clock

1 Gate 40 MHz clock

0x0 Reserved. Must be written with zero. Contains zeros when read.

0x0 Used to set the gate reset controls for the MAC

0 Gates the reset controls from the MAC

1 Do not gate the reset controls from the MAC

0x0 Selects the source of the reset to the USB PHY

0 Determined by bit [12] (USB_POR)

1 Uses the reset from the USB controller

0x0 The software controlled reset to the USB PHY

0 Deassert reset

1 Assert reset

0x0 Used to configure suspension of the USB PHY

0 Allows the USB controller to control the suspend signal to

the USB PHY

1 Forces the suspend signal of the USB PHY to be 0, in suspend

mode

0x0 The software controlled warm reset to the baseband

0 Deassert reset

1 Assert reset

0x0 The software controlled cold reset to the baseband

0 Deassert reset

1 Assert reset

0x0 The software controlled cold reset to clock generation and

miscellaneous logic

0 Deassert reset

1 Assert reset

0x0 The software controlled warm reset to radio

0 Deassert reset

1 Assert reset

0x0 The software controlled cold reset to radio

0 Deassert reset

1 Assert reset

Atheros Communications, Inc.

COMPANY CONFIDENTIAL

AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 45

November 2011 • 45

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