6.2 Reset/Clock Control Register
This section describes the Reset Clock Control
registers for the AR9271. Table 6-3 defines the
offset, type and page location of these registers.
Table 6-3. Reset/Clock Control Registers
Offset
0x0005_0000
0x0005_0004
0x0005_0008
0x0005_000C
0x0005_0010
0x0005_0014
0x0005_001C
0x0005_0020
0x0005_0040
0x0005_0044
0x0005_0048
0x0005_004C
0x0005_0090
Description
General Purpose Timer Register
General Purpose Timer Reload Register
Watchdog Timer Control Register
Watchdog Timer Register
Reset Register
Bootstrap Values
Watchdog Timer Interrupt
General Timer Interrupt
Clock Control Register
Reset and Power Down Control Register
USB PLL Parameter Register
Reset Status Register
Chip Revision ID
Page
page 41
page 41
page 42
page 42
page 42
page 42
page 43
page 43
page 43
page 44
page 46
page 47
page 47
6.2.1 General Purpose Timer Register (RST_GENERAL_TIMER)
Address: 0x0005_0000
Access: Read/Write
This register is a timer that counts down to
zero, sets an interrupt, and then reloads from
the General Timer Reload Register.
Bit
Bit Name Type Reset Description
31:0
TIMER
R/W 0x0 Timer value.
6.2.2 General Purpose Timer Reload Register (RST_GENERAL_TIMER_RELOAD)
Address: 0x0005_0004
Access: Read/Write
This register contains the value that will be
loaded into the General Purpose Timer register
when it decrements to zero.
Bit
Bit Name Type Reset Description
31:0
RELOAD_ R/W 0x0 Timer reload value
VALUE
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 41
November 2011 • 41