4. Digital PHY Block
The digital physical layer (PHY) block is
described in 802.11 draft-n mode and
802.11b/g legacy mode. Transmit and receive
paths are provided and shown as block
diagrams for 802.11 draft-n mode.
4.1 Overview
The digital PHY block is a half-duplex, OFDM,
CCK, DSSS baseband processor compatible
with IEEE 802.11n and 802.11b/g. The AR9281
supports PHY data rates up to 72.2 Mbps in
20- and 150 Mbps in 40-MHz channel modes
and all data rates defined by the IEEE 802.11b/
g standard (1–54Mbps). Modulation schemes
include BPSK, QPSK, 16-QAM, 64-QAM and
forward error correction coding with rates of
1/2, 2/3, 3/4, 5/6.
4.2 802.11n Mode
Frames beginning with training symbols are
used for signal detection, automatic gain
control, frequency offset estimation, symbol
timing, and channel estimation. This process
uses 56 sub-carriers for 20-MHz HT mode: 52
for data transmission and 4 for pilots. It uses
114 sub-carriers for 40-MHz HT mode: 108 for
data transmission and 6 for pilots.
4.2.1 Transmitter (Tx)
Figure 4-1 shows the Tx path digital PHY
802.11n block diagram.
The PCU block initiates transmission. The
digital PHY powers on the digital to analog
converter (DAC) and transmit portions of the
AR9281. The training symbols are a fixed
waveform and are generated within the digital
PHY in parallel with the PCU sending the Tx
header (frame length, data rate, etc.). The PCU
must send transmitted data quickly enough to
prevent buffers in the digital PHY from
becoming empty. The PCU is prevented from
sending data too quickly by pauses generated
within the digital PHY.
Figure 4-1 shows a system with one spatial
data stream. Puncturing and padding are
added to the encoded data. At this point, it
interleaves coded bits across different data
subcarriers followed by the modulation, then
the stream undergoes IFFT processing to
produce time domain signals.
4.2.2 Receiver (Rx)
Figure 4-2 shows the Rx path digital PHY
802.11n block diagram.
Figure 4-1. Digital PHY 802.11n Tx
Figure 4-2. Digital PHY 802.11n Rx
The receiver inverts the transmitter’s steps,
performing a fast fourier transform (FFT),
extracting bits from received constellations, de-
interleaving, accounting for puncturing,
decoding, and descrambling. The Rx block
shows one spatial stream configuration.
Figure 4-2 shows a frequency-domain
equalizer handling degradation due to multi-
path.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 33
November 2011 • 33