Table 3-2. Tx Control Descriptor Format (Words 2–13) (continued)
Word
10
11
Bits
23:0
31:24
23:0
29:24
31:30
12 23:0
29:24
31:30
13 23:0
29:24
31:30
Field Name
antenna_0
RES
antenna_1
tpc_1
RES
antenna_2
tpc_2
RES
antenna_3
tpc_3
RES
Description
Antenna switch for Tx series 0
Reserved
Antenna switch for Tx series 1
Tx power control (TPC) for Tx series 1
These bits pass unchanged to the baseband to control Tx power for the frame.
Reserved
Antenna switch for Tx series 2
Tx power control (TPC) for Tx series 2
These bits pass unchanged to the baseband to control Tx power for the frame.
Reserved
Antenna switch for Tx series 3
Tx power control (TPC) for Tx series 3
These bits pass unchanged to the baseband to control Tx power for the frame.
Reserved
The Tx descriptor format for words 14 through
24 is described in Table 3-3.
Table 3-3. Tx Status Descriptor Format (Words 14–23)
Word Bits
14 7:0
29:8
30
31
Field Name
rssi_ant00
RES
ba_status
RES
Description
Rx ACK signal strength indicator of control channel chain 0.
A value of 0x80 (–128) indicates an invalid number.
Reserved
Block ACK status.
If set, this bit indicates that the ba_bitmap values are valid
Reserved
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 25
November 2011 • 25