A2V64S40 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

A2V64S40

64M Single Data Rate Synchronous DRAM

Unspecified 

A2V64S40CTP

64M Single Data Rate Synchronous DRAM

DQM Control

The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and LDQM is

different during reading and writing.

Reading

When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low, the output

buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer becomes High-Z, and

the corresponding data is not output. However, internal reading operations continue. The latency of UDQM and LDQM

during reading is 2 clocks.

Writing

Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when UDQM and

LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency of UDQM and LDQM

during writing is 0 clock.

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Revision 2.1

Page 28/36

Sep., 2008

Datasheet pdf - http://www.DataSheet4U.net/

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