A2V64S40CTP
64M Single Data Rate Synchronous DRAM
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval
between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by
means of UDQM and LDQM for assurance of the clock defined by tDPL.
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