A2V64S40CTP
64M Single Data Rate Synchronous DRAM
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
High-Z after the /CAS latency from the burst stop command.
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During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to
High-Z at the same clock with the burst stop command.
Revision 2.1
Page 18/36
Sep., 2008
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