A2V64S40 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

A2V64S40

64M Single Data Rate Synchronous DRAM

Unspecified 

A2V64S40CTP

64M Single Data Rate Synchronous DRAM

Power-up sequence

Power-up sequence

The SDRAM should be goes on the following sequence with power up.

The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.

The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.

The CKE and DQM is driven to high between power stabilizes and the initialization sequence.

This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If the sepins go high

before power up, the large current flows from these pins to VDD through the diodes.

Initialization sequence

When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge

command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS)

to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z

during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.

www.DataSheet.co.kr

Revision 2.1

Page 14/36

Sep., 2008

Datasheet pdf - http://www.DataSheet4U.net/

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