ST7263Bxx
I/O ports
9.3
9.3.1
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR register
and specific feature of the I/O port such as ADC input or true open drain.
Port A
Table 11. Port A0, A3, A4, A5, A6, A7 description
PORT A
I/Os
Input(1)
Output
Alternate function
Signal
Condition
PA0
with pull-up push-pull
PA3
with pull-up push-pull
PA4
PA5
PA6(2)
PA7
with pull-up
Push-pull
with pull-up
Push-pull
with pull-up
Push-pull
with pull-up
Push-pull
MCO (Main Clock output) MCO = 1 (MISCR)
Timer EXTCLK
CC1 =1
CC0 = 1 (Timer CR2)
Timer ICAP1
IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
Timer ICAP2
IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
Timer OCMP1
OC1E = 1
IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
Timer OCMP2
OC2E = 1
IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
1. Reset state.
2. Not available on SO24
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration
ALTERNATE 1
OUTPUT
0
ALTERNATE ENABLE
VDD
P-BUFFER
DR
LATCH
DDR
LATCH
DDR SEL
ALTERNATE ENABLE
PULL-UP
VDD
PAD
DR SEL
1
ALTERNATE INPUT
0
N-BUFFER
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
DIODES
Doc ID 7516 Rev 8
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