AR0141CS(2016) View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

AR0141CS
(Rev.:2016)

1/4-Inch Digital Image Sensor

ON Semiconductor 

AR0141CS: 1/4-Inch Digital Image Sensor

Slave Mode

Row Period (TROW)

line_length_pck will determine the number of clock periods per row and the row period

(TROW) when combined with the sensor readout clock. line_length_pck includes both

the active pixels and the horizontal blanking time per row. The sensor utilizes two

readout paths, as seen in Figure 1 on page 4, allowing the sensor to output two pixels

during each pixel clock.

Row Periods Per Frame

frame_length_lines determines the number of row periods (TROW) per frame. This

includes both the active and blanking rows. The minimum vertical blanking value is

defined by the number of OB rows read per frame, two embedded data rows, and two

blank rows.

Minimum frame_length_lines = y---_---a---d---d---r--y-_--_-e--on---dd---d--–-_---iy--n-_--c-a---d+---d--1-r--_---s---t-2a---r---t---+-----1-- + min_vertical_blanking

(EQ 8)

The sensor is configured to output frame information in two embedded data rows by

setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead output

two blank rows. The data configured in the two embedded rows is defined in two

embedded rows of data at the top of the frame by setting R0x3064[7] and two rows of

embedded statistics at the end of the frame by setting R0x3064[7] for exposure calcula-

tions. See the section on Embedded Data and Statistics.

Table 13: Minimum Vertical Blanking Configuration

R0x3180[7:4]

0x8 (Default)

0x4

0x2

OB Rows

8 OB Rows

4 OB Rows

2 OB Rows

min_vertical_blanking1

8 OB + 8 = 16

4 OB + 8 = 12

2 OB + 8 = 10

The locations of the OB rows, embedded rows, and blank rows within the frame readout

are identified in Figure 26: “Slave Mode Active State and Vertical Blanking,” on page 29.

Slave Mode

The slave mode feature of the AR0141CS supports triggering the start of a frame readout

from a VD signal that is supplied from an external device. The slave mode signal allows

for precise control of frame rate and register change updates. The VD signal is an edge

triggered input to the trigger pin and must be at least 3 PIXCLK cycles wide.

AR0141CS/D Rev. 6, 4/16 EN

28

©Semiconductor Components Industries, LLC, 2016.

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