AR0141CS(2016) View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

AR0141CS
(Rev.:2016)

1/4-Inch Digital Image Sensor

ON Semiconductor 

AR0141CS: 1/4-Inch Digital Image Sensor

Sensor PLL

Serial PLL Configuration

Figure 20: PLL for the Serial Interface

F VCO

EXTCLK

(6-50 MHz)

pre_pll_clk_div

2 (1-64)

pll_multiplier

58 (32-384)

vt_sys_clk_div

1 (1, 2, 4, 6, 8,

10, 12, 14, 16)

vt_pix_clk_div

6 (4-16)

CLK_PIX

AR0141CS/D Rev. 6, 4/16 EN

F VCO

op_sys_clk_div

(default = 1)

op_pix_clk_div

12 (8, 10, 12, 14, 16)

CLK_OP

F S E RIA L

1/2

F S E RIA L_CLK

The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per

lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)

configured. To configure the sensor protocol and number of lanes, refer to “Serial

Configuration” on page 16.

Table 8: PLL Parameters for the Serial Interface

Parameter

Symbol

Min

Max

Unit

External Clock

VCO Clock

Readout Clock

Output Serial Data Rate Per Lane

Output Serial Clock Speed Per Lane

EXTCLK

FVCO

CLK_PIX

FSERIAL

FSERIAL_CLK

6

384

300 (HiSPi)

150 (HiSPi)

50

768

74.25

600 (HiSPi)

350(HiSPi)

MHz

MHz

Mpixel/s

Mbps

MHz

Configure the serial output so that it adheres to the following rules:

• The maximum data-rate per lane (FSERIAL) is 600Mbps/lane (HiSPi).

• Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate

matches the peak pixel rate (2 x CLK_PIX).

– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s)

– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s)

Table 9:

Example PLL Configurations for the Serial Interface

Parameter

FVCO

vt_sys_clk_div

vt_pix_clk_div

op_sys_clk_div

4-lane

12-bit

445.5

1

6

1

2-lane

12-bit

445.5

1

12

1

Units

MHz

21

©Semiconductor Components Industries, LLC, 2016.

Share Link: