AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Parallel PLL Configuration
Figure 19: PLL for the Parallel Interface
.
F VCO
EXTCLK
(6-50 MHz)
pre_pll_clk_div
2 (1-64)
pll_multiplier
58 (32-384)
vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10, 12, 14, 16)
vt_pix_clk_div
6 (4-16)
CLK_OP
(Max 74.25 Mp/s)
The maximum output of the parallel interface is 74.25 MPixel/s. The sensor will not use
the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface.
Table 6:
PLL Parameters for the Parallel Interface
Parameter
External Clock
VCO Clock
Output Clock
Symbol
EXTCLK
FVCO
CLK_OP
Min
Max
Unit
6
50
MHz
384
768
MHz
74.25
Mpixel/s
Table 7:
Example PLL Configuration for the Parallel Interface
Parameter
FVCO
vt_sys_clk_div
vt_pix_clk_div
CLK_OP
Output pixel rate
Value
1
6
Output
445.5 MHz (Max)
74.25 MPixel/s (= 445.5 MHz / 6)
74.25 MPixel/s
AR0141CS/D Rev. 6, 4/16 EN
20
©Semiconductor Components Industries, LLC, 2016.