M1A3P1000-1VQG144YI View Datasheet(PDF) -

ProASIC3 Flash Family FPGAs

tEOUT

DQ

E

CLK

tZL, tZH, tHZ, tLZ, tZLS, tZHS

DQ

D

CLK

EOUT

DOUT

PAD

I/O Interface

D

E

EOUT

PAD

50%

tEOUT (R)

50%

tZL

Vtrip

VOL

tEOUT = MAX(tEOUT(r), tEOUT(f))

VCC

50%

tEOUT (F)

50%

tHZ

90% VCCI

VCC

50%

tZH

VCC

VCCI

Vtrip

50%

tLZ

10% VCCI

VCC

D

E 50%

EOUT

PAD

tEOUT (R)

50%

VCC

50%

tZLS

Vtrip

VOL

tEOUT (F)

50%

VOH

VCC

50%

tZHS

Vtrip

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

Revision 13

2- 17

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