M1A3P1000-1VQG144YI View Datasheet(PDF) -

PAD

ProASIC3 Flash Family FPGAs

tPY

tDIN

DQ

Y

DIN

CLK

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

I/O Interface

VIH

PAD

Vtrip

Vtrip

VIL

VCC

Y

GND

50%

tPY

(R)

50%

tPY

(F)

DIN

GND

50%

tDIN

(R)

VCC

tDIN

(F)

Figure 2-3 • Input Buffer Timing Model and Delays (example)

50%

Revision 13

2- 15

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