M1A3P400-FGG144YES View Datasheet(PDF) -

ProASIC3 DC and Switching Characteristics

User I/O Characteristics

Timing Model

LVPECL

(Applicable

to Advanced

I/O Banks only)

I/O Module

(Registered)

tPY = 1.05 ns

DQ

Input LVTTL

Clock

ttIISCULKDQ==00.2.264nnss

tPY = 0.76 ns (Advanced I/O Banks)

I/O Module

(Non-Registered)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

tPY = 1.20 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL (Applicable to

Advanced I/O Banks Only)L

tPD = 0.56 ns

Combinational Cell

tPD = 0.49 ns

tDP = 1.34 ns

I/O Module

(Non-Registered)

Y

LVTTLOHiugthpustledwrivreatsetrength = 12 mA

tPD = 0.87 ns

tDP = 2.64 ns (Advanced I/O Banks)

Combinational Cell

I/O Module

(Non-Registered)

Y

tPD = 0.47 ns

Combinational Cell

LVTTLOHiugthpustledwrivreatsetrength = 8 mA

tDP = 3.66 ns (Advanced I/O Banks)

I/O Module

(Non-Registered)

Y

tPD = 0.47 ns

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

tDP = 3.97 ns (Advanced I/O Banks)

Register Cell Combinational Cell Register Cell

DQ

Y

DQ

tPD = 0.47 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

Input LVTTL

Clock

tCLKQ = 0.55 ns

tSUD = 0.43 ns

Input LVTTL

Clock

I/O Module

(Registered)

DQ

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

tDP = 2.64 ns

(Advanced I/O Banks)

tOCLKQ = 0.59 ns

tOSUD = 0.31 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tPY = 0.76 ns

(Advanced I/O Banks)

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case

VCC = 1.425 V

2-14

Revision 13

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