MPC9893 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
MPC9893 Datasheet PDF : 14 Pages
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MPC9893 Data Sheet
tSK(O)
VCC
VCC 2
GND
VCC
VCC 2
GND
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
Figure 12. Output-to-Output Skew tSK(O)
tP
T0
DC = tP/T0 x 100%
VCC
VCC 2
GND
The time from the PLL controlled edge to the noncontrolled edge, divided by
the time between PLL controlled edges, expressed as a percentage
Figure 14. Output Duty Cycle (DC)
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
CLK0,
CLK1
FB
t()
VCC
VCC 2
GND
VCC
VCC 2
GND
Figure 13. Propagation Delay (t(), static phase
offset) Test Reference
CCLK0, 1
FB
TJIT() = |T0–T1mean|
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample
of cycles
Figure 15. I/O Jitter
TN
TN+1
TJIT(CC) = |TN–TN+1|
The variation in cycle time of a signal between adjacent cycles, over a random sample
of adjacent cycle pairs
Figure 16. Cycle-to-Cycle Jitter
T0
TJIT(PER) = |TN–1/f0|
The deviation in cycle time of a signal with respect to the ideal period over a random
sample of cycles
Figure 17. Period Jitter
VCC=3.3 V
2.4
VCC=2.5 V
1.8
0.55
0.6
tF
tR
Figure 18. Output Transition Time Test Reference
MPC9893 REVISION 8 3/16/16
11
©2016 Integrated Device Technology, Inc.
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