CAT25010L View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part Name

Description

Manufacturer

CAT25010L

1K/2K/4K SPI Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT25010/20/40

STATUS REGISTER

The Status Register indicates the status of the device.

The RDY (Ready) bit indicates whether the CAT25010/

20/40 is busy with a write operation. When set to 1 a

write cycle is in progress and when set to 0 the device

indicates it is ready. This bit is read only. The WEL (Write

Enable) bit indicates the status of the write enable latch.

When set to 1, the device is in a Write Enable state and

when set to 0 the device is in a Write Disable state. The

WEL bit can only be set by the WREN instruction and can

be reset by the WRDI instruction.

The BP0 and BP1 (Block Protect) bits indicate which

blocks are currently protected. These bits are set by the

user issuing the WRSR instruction. The user is allowed

to protect quarter of the memory, half of the memory or

the entire memory by setting these bits. Once protected,

the user may only read from the protected portion of the

array. These bits are non-volatile.

Figure 2. WREN Instruction Timing

CS

DEVICE OPERATION

Write Enable and Disable

The CAT25010/20/40 contains a write enable latch. This

latch must be set before any write operation. The device

powers up in a write disable state when Vcc is applied.

WREN instruction will enable writes (set the latch) to the

device. If WP pin is held low, the write enable latch is

reset to the write disabe state, regardless of the WREN

Instruction. WRDI instruction will disable writes (reset

the latch) to the device. Disabling writes will protect the

device against inadvertent writes.

READ Sequence

The part is selected by pulling CS low. The 8-bit read

instruction is transmitted to the CAT25010/20/40, followed

by the 8-bit address for CAT25010/20/40 (for the 25040,

bit 3 of the read data instruction contains address A8).

After the correct read instruction and address are sent,

the data stored in the memory at the selected address is

shifted out on the SO pin. The data stored in the memory

at the next address can be read sequentially by continuing

SK

SI

SO

Note: Dashed Line= mode (1, 1) – – – – –

0 0 0 0 0 1 10

HIGH IMPEDANCE

Figure 3. WRDI Instruction Timing

CS

SK

SI

SO

Note: Dashed Line= mode (1, 1) – – – – –

0 0 0 0 0 1 00

HIGH IMPEDANCE

Doc. No. 1006, Rev. L

6

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