AD7366-5ARUZ-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7366-5ARUZ-REEL7 Datasheet PDF : 17 Pages
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AD7366
Preliminary Technical Data
SERIAL INTERFACE
Figure 9 shows the detailed timing diagram for serial inter-
facing to the AD7366. On the falling edge of CONVST the
AD7366 will simultaneously convert the selected channels.
These conversions are performed using the on-chip oscillator.
After the falling edge of CONVST the BUSY signal goes high,
indicating the conversion has started. It returns low once the
conversion has been completed. The data can now be read from
the DOUT pins.
CS and SCLK signals are required to transfer data from the
AD7366. The AD7366 has two output pins corresponding to
each ADC. Data can be read from the AD7366 using both
DOUTA & DOUTB, alternatively a single output pin of your
choice can be used. The SCLK input signal provides the
clock source for the serial interface. The CS goes low to
access data from the AD7366. The falling edge of CS takes
the bus out of three-state and clocks out the MSB of the
conversion result. The data stream consists of 12 bits of data
MSB first. The first bit of the conversion result is valid on the
first SCLK falling edge after the CS falling edge. The
subsequent 11 bits of data are clocked out on the falling edge
of the SCLK signal. A minimum of 12 Clock pulses must be
provided to AD7366 to access each conversion result. Figure
CS
9 shows how a 12 SCLK read is used to access the conversion
results.
On the rising edge of CS, the conversion will be terminated
and DOUTA and DOUTB go back into three-state. If CS is not
brought high, but is instead held low for a further 12 SCLK
cycles on either DOUTA or DOUTB, the data from the other
ADC follows on the DOUT pin. This is illustrated in Figure 10
where the case for DOUTA is shown. In this case, the DOUT
line in use goes back into three-state on the rising edge of CS
If the falling edge of SCLK coincides with the falling edge of
CS, then the falling edge of SCLK is not acknowledged by
the AD7366, and the next falling edge of the SCLK will be
the first registered after the falling edges of the CS.
The CS pin can be brought low before the BUSY signal goes
low to indicate the end of a conversion. The data bus is bought
out of three-state by taking the CS pin low. This feature can be
utilized to ensure that the MSB is valid on the falling edge of
BUSY by bring CS low a minimum of t4 nanoseconds before the
BUSY signal goes low. The dotted CS line in Figure 7 illustrates
this.
SCLK
t8
1
2
3
4
5
t4
t5
t6
DOUTA
DB10
DB9
DB8
DOUTB
3-STATE
DB11
t7
DB2
DB1
Figure 9. Serial Interface Timing diagram
12
t9
DB0
3-STATE
CS
SCLK
1
2
3
t4
DOUTA THREE-
DB10A
STATE DB11A
DB9A
t8
4
5
t7
t5
10
11
12
13
t6
DB1A
DB0A DB11B DB10B
Figure 10. Reading Data from Both ADC’s on ONE DOUT Line with 28 SCLK’s
DB1B
24
t10
DB0B
THREE-
STATE
Rev. PrG | Page 16 of 17
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