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5962-8944501JA View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
5962-8944501JA High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter Texas-Instruments
Texas Instruments Texas-Instruments
5962-8944501JA Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CD54HC4059, CD74HC4059
The counter should always be put in the master preset mode
before the ÷5 mode is selected. Whenever the master preset
mode is used, control signals Kb = “low” and Kc = “low” must
be applied for at least 3 full clock pulses.
Pinout
After Preset Mode inputs have been changed to one of the ÷
modes, the next positive-going clock transition changes an
internal flip-flop so that the countdown can begin at the
second positive-going clock transition. Thus, after an MP
(Master Preset) mode, there is always one extra count
before the output goes high. Figure 1 illustrates a total count
of 3 (÷8 mode). If the Master Preset mode is started two
clock cycles or less before an output pulse, the output pulse
will appear at the time due. If the Master Preset Mode is not
used, the counter jumps back to the “Jam” count when the
output pulse appears.
A “high” on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to “low”.
If the Latch Enable is “low”, the output pulse will remain high
for only one cycle of the clock-input signal.
CD54HC4059
(CERDIP)
CD74HC4059
(PDIP, SOIC)
TOP VIEW
CP 1
LE 2
J1 3
J2 4
J3 5
J4 6
J16 7
J15 8
J14 9
J13 10
Kc 11
GND 12
24 VCC
23 Q
22 J5
21 J6
20 J7
19 J8
18 J9
17 J10
16 J11
15 J12
14 Ka
13 Kb
Functional Diagram
J1 - J16
CP
Ka
Kb
Q=
f--NI--N---
Kc
LE
TRUTH TABLE
COUNTER RANGE
MODE SELECT INPUT
FIRST COUNTING SECTION
LAST COUNTING SECTION
DESIGN EXTENDED
CAN BE (NOTE 1)
CAN BE (NOTE 1)
PRESET
JAM
PRESET
JAM
MODE TO A MAX INPUTS
MODE TO A MAX INPUTS
Ka
Kb
Kc DIVIDES-BY
OF:
USED: DIVIDES-BY OF:
USED:
MAX
H
H
H
2
1
J1
8
7
J2, J3, J4 15,999
MAX
17,331
L
H
H
4
3
J1, J2
4
3
J3, J4
15,999
18,663
H
L
H
5
4
J1, J2, J3
2
(Note 2)
1
J4
9,999
13,329
L
L
H
8
7
J1, J2, J3
2
1
J4
15,999
21,327
H
H
L
10
9
J1, J2, J3, J4
1
0
-
9,999
16,659
X
L
L
Master Preset
Master Preset
-
-
X = Don’t care
NOTES:
1. J1 = Least Significant Bit. J4 = Most Significant Bit.
2. Operation in the 5mode (1st counting section) requires going through the Master Preset mode prior to going into the 5mode. At power
turn-on, Kc must be “low” for a period of 3 input clock pulses after VCC reaches a minimum of 3V.
2
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