NXP Semiconductors
LPC8N04
32-bit ARM Cortex-M0+ microcontroller
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
tcy(clk)
tv(Q)
DATA VALID
DATA VALID
DATA VALID
tSU;DAT
tHD;DAT
DATA VALID
th(Q)
CPHA = 1
MOSI
MISO
tv(Q)
DATA VALID
DATA VALID
DATA VALID
tSU;DAT tHD;DAT
DATA VALID
th(Q)
Fig 12. SPI master timing in SPI mode
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
tcy(clk)
DATA VALID
tv(Q)
DATA VALID
tSU;DAT tHD;DAT
DATA VALID
DATA VALID
th(Q)
CPHA = 0
aaa-024226
CPHA = 1
LPC8N04
Product data sheet
MOSI
MISO
DATA VALID
tv(Q)
DATA VALID
tSU;DAT tHD;DAT
DATA VALID
DATA VALID
th(Q)
Fig 13. SPI slave timing in SPI mode
CPHA = 0
aaa-024227
All information provided in this document is subject to legal disclaimers.
Rev. 1.3 — 15 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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