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74LV175 View Datasheet(PDF) - Philips Electronics

Part Name
Description
Manufacturer
74LV175 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Product specification
74LV175
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Four edge-triggered D flip-flops
Output capability: standard
ICC category: MSI
DESCRIPTION
The 74LV175 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT175.
The 74LV175 has four edge-triggered, D-type flip-flops with
individual D inputs and both Q and Q outputs. The common clock
(CP) and master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
set-up time prior to the LOW-to-HIGH clock transition, is transferred
to the corresponding output (Qn) of the flip-flop.
All Qn outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true and
complement outputs are required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
CP to Qn, Qn
MR to Qn, Qn
CL = 15 pF;
VCC = 3.3 V
fmax
Maximum clock frequency
CI
Input capacitance
CPD
Power dissipation capacitance per flip-flop
VCC = 3.3 V
VI = GND to VCC1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL VCC2 fo) = sum of the outputs.
TYPICAL
16
14
77
3.5
32
UNIT
ns
ns
MHz
pF
pF
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV175 N
74LV175 D
74LV175 DB
74LV175 PW
NORTH AMERICA
74LV175 N
74LV175 D
74LV175 DB
74LV175PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
SV00596
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Master reset input (active LOW)
2, 7, 10, 15
3, 6, 11, 14
4, 5, 12, 13
8
Q0 to Q3
Q0 to Q3
D0 to D3
GND
Flip-flop outputs
Complementary flip-flop outputs
Data inputs
Ground (0 V)
9
CP
Clock input
(LOW-to-HIGH, edge-triggered)
16
VCC
Positive supply voltage
1998 May 20
2
853–1926 19422
 

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