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74ALVCH16240TTR(2003) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
74ALVCH16240TTR Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
74ALVCH16240
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
tPD = 3.9 ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 5.3 ns (MAX.) at VCC = 2.3 to 2.7V
tPD = 7.5 ns (MAX.) at VCC = 1.65V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3.0V
|IOH| = IOL = 18mA (MIN) at VCC = 2.3V
|IOH| = IOL = 4mA (MIN) at VCC = 1.65V
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V
s BUS HOLD PROVIDED ON DATA INPUTS
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16240
s LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16240 is a low voltage CMOS 16
BIT BUS BUFFER (INVERTED) fabricated with
sub-micron silicon gate and five-layer metal wiring
C2MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6V applications; it can
be interfaced to 3.6V signal environment for both
inputs and outputs.
Any nG output control governs four BUS
BUFFERS. Output Enable input (nG) tied together
gives full 16-bit operation.
When nG is LOW, the outputs are enabled. When
nG is HIGH, the output are in high impedance
state.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74ALVCH16240TTR
February 2003
1/10
 

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