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DM74ALS244ASJ View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
DM74ALS244ASJ
Fairchild
Fairchild Semiconductor Fairchild
DM74ALS244ASJ Datasheet PDF : 6 Pages
1 2 3 4 5 6
September 1986
Revised February 2000
DM74ALS244A
Octal 3-STATE Bus Driver
General Description
This octal 3-STATE bus driver is designed to provide the
designer with flexibility in implementing a bus interface with
memory, microprocessor, or communication systems. This
device offers 64-extended temperature Grade product
guaranteeing performance from 40°C to +85°C. The out-
put 3-STATE gating control is organized into two separate
groups of four buffers, and both control inputs enable the
respective outputs when set logic LOW. The 3-STATE cir-
cuitry contains a feature that maintains the buffer outputs in
3-STATE (high impedance state) during power supply
ramp-up or ramp-down. This eliminates bus glitching prob-
lems that arise during power-up and power-down.
Features
s Advanced low power oxide-isolated ion-implanted
Schottky TTL process
s Functional and pin compatible with the 74LS counterpart
s Improved switching performance with less power dissi-
pation compared with the 74LS counterpart
s Switching response specified into 500and 50 pF load
s Switching response specifications guaranteed over full
temperature and VCC supply range
s PNP input design reduces input loading
Ordering Code:
Order Number Package Number
Package Description
DM74ALS244AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS244ASJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS244AMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS244AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Function Table
Input
Output
G
A
Y
L
L
L
L
H
H
H
X
Z
H = HIGH Level Logic State
L = LOW Level Logic State
X = Don't Care (Either LOW or HIGH Level Logic State)
Z = High Impedance (OFF) State
© 2000 Fairchild Semiconductor Corporation DS006212
www.fairchildsemi.com
 

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