74ACTQ373SCX_99 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
74ACTQ373SCX_99 Datasheet PDF : 10 Pages
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July 1989
Revised November 1999
74ACQ373 • 74ACTQ373
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACQ/ACTQ373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The latches
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input tim-
ing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the HIGH impedance state.
The ACQ/ACTQ373 utilizes Fairchild Quiet Series tech-
nology to guarantee quiet output switching and improve
dynamic threshold performance. features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch up immunity
s Eight latches in a single package
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT373
Ordering Code:
Order Number Package Number
Package Description
74ACQ373SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ373PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide
74ACTQ373SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQT373QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74ACTQ373PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010237
www.fairchildsemi.com
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