80C186EB View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
80C186EB Datasheet PDF : 59 Pages
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80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
VCC
VSS
CLKIN
OSCOUT
CLKOUT
RESIN
RESOUT
PDTMR
NMI
TEST BUSY
(TEST)
AD15 0
(AD7 0)
Pin
Type
P
G
I
O
O
I
O
IO
I
I
IO
Input
Type
A(E)
A(L)
A(L)
A(E)
A(E)
S(L)
Table 3 Pin Descriptions
Output
States
Description
POWER connections consist of four pins which must be
shorted externally to a VCC board plane
GROUND connections consist of six pins which must be
shorted externally to a VSS board plane
CLocK INput is an input for an external clock An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For crystal
operation CLKIN (along with OSCOUT) are the crystal
connections to an internal Pierce oscillator
H(Q)
R(Q)
P(Q)
OSCillator OUTput is only used when using a crystal to
generate the external clock OSCOUT (along with CLKIN)
are the crystal connections to an internal Pierce oscillator
This pin is not to be used as 2X clock output for non-crystal
applications (i e this pin is N C for non-crystal applications)
OSCOUT does not float in ONCE mode
H(Q)
R(Q)
P(Q)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
(CLKIN) frequency CLKOUT has a 50% duty cycle and
transistions every falling edge of CLKIN
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state All
pins will be driven to a known state and RESOUT will also
be driven active The rising edge (low-to-high) transition
synchronizes CLKOUT with CLKIN before the processor
begins fetching opcodes at memory location 0FFFF0H
H(0) RESet OUTput that indicates the processor is currently in
R(1) the reset state RESOUT will remain active as long as RESIN
P(0) remains active
H(WH)
R(Z)
P(1)
Power-Down TiMeR pin (normally connected to an external
capacitor) that determines the amount of time the processor
waits after an exit from power down before resuming normal
operation The duration of time required will depend on the
startup characteristics of the crystal oscillator
Non-Maskable Interrupt input causes a TYPE-2 interrupt to
be serviced by the CPU NMI is latched internally
TEST is used during the execution of the WAIT instruction to
suspend CPU operation until the pin is sampled active
(LOW) TEST is alternately known as BUSY when interfacing
with an 80C187 numerics coprocessor (80C186EB only)
H(Z)
R(Z)
P(X)
These pins provide a multiplexed Address and Data bus
During the address phase of the bus cycle address bits 0
through 15 (0 through 7 on the 80C188EB) are presented on
the bus and can be latched using ALE 8- or 16-bit data
information is transferred during the data phase of the bus
cycle
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
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