Philips Semiconductors
P-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Drain-source breakdown voltage
−ID = 10 µA; VGS = 0
Drain-source leakage current
−VDS = 48 V; VGS = 0
Gate-source leakage current
± VGS = 20 V; VDS = 0
Gate threshold voltage
−ID = 1 mA; VDS = VGS
Drain-source ON-resistance
−ID = 200 mA ; −VGS = 10 V
Transfer admittance
−ID = 200 mA; −VDS = 15 V
Input capacitance at f = 1 MHz;
−VDS = 10 V; VGS = 0
Output capacitance at f = 1 MHz;
−VDS = 10 V; VGS = 0
Feedback capacitance at f = 1 MHz;
−VDS = 10 V; VGS = 0
Switching times (see Figs 2 and 3)
−ID = 200 mA; −VDD = 50 V;
−VGS = 0 to 10 V
−V(BR)DSS
−IDSS
±IGSS
−VGS(th)
RDS(on)
Yfs
Ciss
Coss
Crss
ton
toff
min.
max.
max.
min.
max.
typ.
max.
min.
typ.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
Product specification
BSP205
60 V
1.0 µA
100 nA
1.5 V
3.5 V
7.5 Ω
10 Ω
60 mS
125 mS
30 pF
45 pF
20 pF
30 pF
5 pF
10 pF
3 ns
6 ns
10 ns
15 ns
April 1995
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