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HCF40193M013TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
HCF40193M013TR Datasheet PDF : 12 Pages
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HCF40193B
PRESETTABLE UP/DOWN COUNTERS
(DUAL CLOCK WITH RESET) BINARY TYPE
s INDIVIDUAL CLOCK LINES FOR COUNTING
UP OR COUNTING DOWN
s SYNCHRONOUS HIGH-SPEED CARRY AND
BORROW PROPAGATION DELAYS FOR
CASCADING
s ASYNCHRONOUS RESET AND PRESET
CAPABILITY
s MEDIUM-SPEED OPERATION - fCL = 8MHz
(typ.) AT 10 V
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s QUIESCENT CURRENT SPECIF. UP TO 20V
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40193B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40193B Presettable Binary Up/Down Counter
consists of 4 synchronously clocked, GATED "D"
type flip-flops connected as a counter. The inputs
consist of four individual jam lines, a PRESET
ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY
PIN CONNECTION
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF40193BEY
HCF40193BM1
T&R
HCF40193M013TR
and BORROW outputs for multiple-stage counting
schemes are provided. The counter is cleared so
that all outputs are in a low state by a high on the
RESET line. A RESET is accomplished
asynchronously with the clock. Each output is
individually programmable asynchronously with
the clock to the level on the corresponding jam
input when the PRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP
line is high. The CARRY and BORROW signals
are high when the counter counts up or down. The
CARRY signal goes low one-half clock cycle after
the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low
September 2002
1/12
 

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