2EZ75_ View Datasheet(PDF) - PANJIT INTERNATIONAL
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2EZ75_ Datasheet PDF : 5 Pages
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APPLICATION NOTE:
Since the actual voltage available from a given zener
diode is temperature dependent, it is necessary to
determine junction temperature under any set of
operating conditions in order to calculate its value. The
following procedure is recommended:
Lead Temperature, TL, should be determined from:
TL = £c LAPD + TA
£c LA is the lead-to-ambient thermal resistance (¢J /W)
and PD is the power dissipation. The value for £c LA will
vary and depends on the device mounting method.
£c LA is generally 30-40 ¢J /W for the various chips and
tie points in common use and for printed circuit board
wiring.
The temperature of the lead can also be measured using
a thermocouple placed on the lead as close as possible to
the tie point. The thermal mass connected to the tie point
is normally large enough so that it will not significantly
respond to heat surges generated in the diode as a result
of pulsed operation once steady-state conditions are
achieved. Using the measured value of TL, the junction
temperature may be determined by:
TJ = TL + £GTJL
£GTJL is the increase in junction temperature above the
lead temperature and may be found from Figure 2 for a
train of power pulses or from Figure 10 for dc power.
£G TJL = £c LAPD
For worst-case design, using expected limits of Iz, limits
of PD and the extremes of TJ (£GTJL ) may be estimated.
Changes in voltage, Vz, can then be found from:
£GV = £c VZ £GTJ
£c VZ , the zener voltage temperature coefficient, is
found from Figures 5 and 6.
Under high power-pulse operation, the zener voltage
will vary with time and may also be affected significantly
be the zener resistance. For best regulation, keep current
excursions as low as possible.
Data of Figure 2 should not be used to compute surge
capability. Surge limitations are given in Figure 3. They
are lower than would be expected by considering only
junction temperature, as current crowding effects cause
temperatures to be extremely high in small spots resulting
in device degradation should the limits of Figure 3 be
exceeded.
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