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74LVT162240MTD View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
74LVT162240MTD Datasheet PDF : 6 Pages
1 2 3 4 5 6
Logic Symbol
Pin Descriptions
Connection Diagram
Functional Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE standard outputs. The device is nib-
ble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins may be
shorted together to obtain full 16-bit operation. The
Logic Diagram
Pin Names
Description
OEn
I0I15
O0O15
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
Truth Table
Inputs
OE1
I0I3
L
L
L
H
H
X
Inputs
OE2
I4I7
L
L
L
H
H
X
Inputs
OE3
I8I11
L
L
L
H
H
X
Inputs
OE4
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
I12I15
L
H
X
Outputs
O0O3
H
L
Z
Outputs
O4O7
H
L
Z
Outputs
O8O11
H
L
Z
Outputs
O12O15
H
L
Z
3-STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW, the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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