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74ALVC162244GX View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
74ALVC162244GX Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistor in Outputs Fairchild
Fairchild Semiconductor Fairchild
74ALVC162244GX Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
November 2001
Revised November 2001
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Series Resistor in Outputs
General Description
The ALVC162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC162244 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V. The
74ALVC162244 is also designed with 26series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26series resistors in outputs
s tPD
3.8 ns max for 3.0V to 3.6V VCC
4.3 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
Ordering Code:
Order Number Package Number
Package Description
(Note 2)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Note 3)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500696
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