ADM1485AR View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADM1485AR Datasheet PDF : 8 Pages
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ADM1485–SPECIFICATIONS (VCC = +5 V ؎ 5%. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
DRIVER
Differential Output Voltage, VOD
VOD3
∆|VOD| for Complementary Output States
Common-Mode Output Voltage VOC
∆|VOD| for Complementary Output States
Output Short Circuit Current (VOUT = High)
Output Short Circuit Current (VOUT = Low)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, ∆VTH
Input Resistance
Input Current (A, B)
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short Circuit Output Current
Tristate Output Leakage Current
POWER SUPPLY CURRENT
ICC (Outputs Enabled)
ICC (Outputs Disabled)
Specifications subject to change without notice.
Min Typ Max
5.0
2.0
5.0
1.5
5.0
1.5
5.0
0.2
3
0.2
35
250
35
250
0.8
2.0
± 1.0
–0.2
+0.2
70
12
+1
–0.8
±1
0.4
4.0
7
85
± 1.0
1.35 2.2
0.7 1
Unit Test Conditions/Comments
V
R = ∞, Figure 1
V
VCC = 5 V, R = 50 Ω (RS-422), Figure 1
V
R = 27 Ω (RS-485), Figure 1
V
VTST = –7 V to +12 V, Figure 2
V
R = 27 Ω or 50 Ω, Figure 1
V
R = 27 Ω or 50 Ω, Figure 1
V
R = 27 Ω or 50 Ω
mA –7 V ≤ VO ≤ +12 V
mA –7 V ≤ VO ≤ +12 V
V
V
µA
V
–7 V ≤ VCM ≤ +12 V
mV VCM = 0 V
kΩ –7 V ≤ VCM ≤ +12 V
mA VIN = 12 V
mA VIN = –7 V
µA
V
IOUT = +4.0 mA
V
IOUT = –4.0 mA
mA VOUT = GND or VCC
µA 0.4 V ≤ VOUT ≤ +2.4 V
mA Outputs Unloaded, Digital Inputs = GND or VCC
mA Outputs Unloaded, Digital Inputs = GND or VCC
TIMING SPECIFICATIONS (VCC = +5 V ؎ 5%. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output TPLH, TPHL 2
10
15
ns RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3
Driver O/P to O/P TSKEW
0
5
ns
RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3
Driver Rise/Fall Time TR, TF
2
10
ns
RL Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 3
Driver Enable to Output Valid
10 25 ns
Driver Disable Timing
10 25 ns
RECEIVER
Propagation Delay Input to Output TPLH, TPHL 18 25
40
ns CL = 15 pF, Figure 5
Skew |TPLH–TPHL|
0
5
ns
Receiver Enable TEN1
Receiver Disable TEN2
15 25 ns Figure 6
15 25 ns Figure 6
Specifications subject to change without notice.
–2–
REV. A
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