M74HC109_92 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M74HC109_92

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

STMicroelectronics 

M54HC109

M74HC109

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

. HIGH SPEED

fMAX = 63 MHz (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 2 µA (MAX.) AT TA = 25 °C

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS109

DESCRIPTION

The M54/74HC109 is a high speed CMOS DUAL J-

K FLIP-FLOP WITH PRESET AND CLEAR fabri-

cated in silicon gate C2MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

In accordance with the logic level on the J and K

input is device changes state on positive going tran-

sitions of the clock pulse. CLEAR and PRESET are

independent of the clock and accomplished by a low

logic level on the corresponding input.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M 54HC 10 9F 1R

M 74H C1 09 M1 R

M 74HC 10 9B 1R

M 74H C1 09 C1 R

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

December 1992

NC =

No Internal

Connection

1/11

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