T-8208-BAL-DT View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

T-8208-BAL-DT

CelXpres™ ATM Interconnect

Agere -> LSI Corporation 

CelXpres T8208

ATM Interconnect

Advance Data Sheet

September 2001

List of Tables (continued)

Tables

Pages

Table 156. SDRAM Interrupt Enable (SIE) (0404h) ................................................................................................179

Table 157. SDRAM Configuration (SCF) (0408h) ...................................................................................................180

Table 158. Refresh (RFRSH) (0410h) .....................................................................................................................181

Table 159. Refresh Lateness (RFRSHL) (0412h) ...................................................................................................181

Table 160. Idle State 1 (IS1) (0420h) ......................................................................................................................181

Table 161. Idle State 2 (IS2) (0422h) ......................................................................................................................181

Table 162. Manual Access State 1 (MAS1) (0424h) ...............................................................................................182

Table 163. Manual Access State 2 (MAS2) (0426h) ...............................................................................................182

Table 164. SDRAM Interrupt Service Request 7 (SISR7) (0430h) .........................................................................183

Table 165. SDRAM Interrupt Service Request 6 (SISR6) (0432h) .........................................................................183

Table 166. SDRAM Interrupt Service Request 5 (SISR5) (0434h) .........................................................................183

Table 167. SDRAM Interrupt Service Request 4 (SISR4) (0436h) ......................................................................... 183

Table 168. SDRAM Interrupt Service Request 3 (SISR3) (0438h) .........................................................................184

Table 169. SDRAM Interrupt Service Request 2 (SISR2) (043Ah) .........................................................................184

Table 170. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) .........................................................................184

Table 171. SDRAM Interrupt Service Request 0 (SISR0) (043Eh) .........................................................................184

Table 172. Queue X (QX) (0440h to 053Eh) ...........................................................................................................185

Table 173. Queue X Definition Structure (QXDEF) (2000h to 2FFEh) ....................................................................187

Table 174. Control Cell Receive Extended Memory (CCRXEM) (07FCh to 0832h) ................................................190

Table 175. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) ................................................190

Table 176. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh) ...................191

Table 177. PHY Port X Multicast Memory (PPXMM) (0C20h to 0FFEh) .................................................................192

Table 178. PPD Memory (PPDM) (1000h to 13FEh) ..............................................................................................193

Table 179. Queue X Dropped Cell Count (QXDCC) (3000h to 31FEh) .................................................................194

Table 180. Translation RAM Memory (TRAM) (100000h to 17FFFEh) ....................................................................197

Table 181. SDRAM (SDRAM) (2000000h to 3FFFFFEh) .......................................................................................197

Table 182. Maximum Rating Parameters and Values ..............................................................................................198

Table 183. Recommended Operating Conditions ....................................................................................................198

Table 184. HBM ESD Threshold ..............................................................................................................................198

Table 185. Crystal Specifications ............................................................................................................................199

Table 186. External Clock Requirements .................................................................................................................199

Table 187. dc Electrical Characteristics ..................................................................................................................200

Table 188. Input Clocks ..........................................................................................................................................201

Table 189. Output Clocks ........................................................................................................................................201

Table 190. Nonmultiplexed Intel Mode Write Access Timing ..................................................................................203

Table 191. Nonmultiplexed Intel Mode Read Access Timing ..................................................................................203

Table 192. Motorola Mode Write Access Timing .....................................................................................................205

Table 193. Motorola Mode Read Access Timing .....................................................................................................205

Table 194. Multiplexed Intel Mode Write Access Timing .........................................................................................207

Table 195. Multiplexed Intel Mode Read Access Timing .........................................................................................207

Table 196. TX UTOPIA Timing (70 pF Load on Outputs) .......................................................................................208

Table 197. RX UTOPIA Timing (70 pF Load on Outputs) .......................................................................... ............208

Table 198. External LUT Memory Read Timing (cyc_per_acc = 2) ........................................................................210

Table 199. External LUT Memory Read Timing (cyc_per_acc = 3) ........................................................................210

Table 200. External LUT Memory Write Timing (cyc_per_acc = 2) ........................................................................210

Table 201. External LUT Memory Write Timing (cyc_per_acc = 3) ........................................................................210

Table 202. Cell Bus Timing .....................................................................................................................................211

Table 203. SDRAM Interface Timing .......................................................................................................................212

8

Agere Systems Inc.

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