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T-8208-BAL-DB Просмотр технического описания (PDF) - Agere -> LSI Corporation

Номер в каталогеКомпоненты Описаниепроизводитель
T-8208-BAL-DB CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DB Datasheet PDF : 214 Pages
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Advance Data Sheet
September 2001
CelXpresTM T8208
ATM Interconnect
1 Product Overview
1.1 Features
s OC-12 data throughput on UTOPIA (16-bit)
(independently on RX and TX UTOPIA)
s Shared UTOPIA mode
s UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level
handshake interface (ATM or PHY layers)
s Multi-PHY (MPHY) operation
s Programmable ATM layer supports up to 64 PHY
s Egress SDRAM buffer support to extend UTOPIA
output priority queues for 32K to 512K cells:
— 128 queues configurable up to four queues per
PHY with programmable sizes
— Programmable number of UTOPIA output
queues with four levels of priority
s Support of ATM traffic management via partial
packet discard (PPD), forward explicit congestion
notification (FECN), and the cell loss priority (CLP)
s Programmable slew rate GTL+ I/O:
— Programmable as bus arbiter
— 1.7 Gbits/s cell bus operation
s Flexible per port cell counters
s Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
s Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow-control (GFC) insertion
s Optional sourcing of cell bus clocks from device
s LUT bypass option
s TX UTOPIA cell buffer increased to 256 cells for
better queue management with SDRAM queue
bypass option
s Ability for cell bus arbiter to mask devices on the
cell bus
s Ability to modify cell bus priority based on RX PHY
FIFO thresholds
s Programmable priority for control/data cells trans-
mission onto cell bus
s Microprocessor access to all headers of control
s Ability to clear counters on read
s Simplified looping to any system device with a sin-
gle register programming
s UTOPIA clock sourcing with additional settings
s Programmable operations and maintenance and
resource management (OAM/RM) cell routing
s Support of multicast and broadcast cells per PHY
s Optional monitoring of misrouted cells
s Counters for dropped cells per queue
s Digital loopback before cell bus
s Microprocessor interface, supporting both Motor-
ola® and Intel® modes (multiplexed and nonmulti-
s Control cell transmission and reception through
microprocessor port
s Single 3.3 V power supply
s 3.3 V TTL I/O (5 V tolerant)
s 272-pin plastic ball grid array (PBGA) package
s Industrial temperature range (–40 °C to +85 °C)
s Hot insertion capability
s Eight GPIO pins
s JTAG support
s Compatible with Transwitch CellBus®
1.2 Applications
s Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
s Access gateways
s Access multiplexers/concentrators
s Multiservice platforms
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