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M41T56SH6 View Datasheet(PDF) - STMicroelectronics

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M41T56SH6 Datasheet PDF : 25 Pages
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M41T56
Figure 12. Alternative READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X P
BUS ACTIVITY:
SLAVE
ADDRESS
WRITE Mode
In this mode the master transmitter transmits to
the M41T56 slave receiver. Bus protocol is shown
in Figure 13., page 10. Following the START con-
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure 10).
Figure 13. WRITE Mode Sequence
AI00895
Data Retention Mode
With valid VCC applied, the M41T56 can be ac-
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T56 will automatically deselect, write protect-
ing itself when VCC falls between VPFD (max) and
VPFD (min). This is accomplished by internally in-
hibiting access to the clock registers and SRAM.
When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the battery and the clock reg-
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC.
For a further more detailed review of battery life-
time calculations, please see Application Note
AN1012.
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (n)
DATA n
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n+1
DATA n+X P
AI00591
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