ML145406EP View Datasheet(PDF) - LANSDALE Semiconductor Inc.
Part Name
Description
Manufacturer
ML145406EP Datasheet PDF : 10 Pages
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ML145406
LANSDALE Semiconductor, Inc.
1
VDD
14
DI1
16
VCC
3
Tx1
12 DI2
Tx2 5
Vin = ± 2 V
10 DI3
Tx3 7
VSS GND
89
Rout
=
Vin
I
Figure 1. Power–Off Source Resistance (Drivers)
DRIVERS
DI1–DI3
50%
Tx1–Tx3 90%
tPHL
tf
10%
tPLH
3V
0V
tr
VOH
VOL
RECEIVERS
Rx1–Rx3 50%
90%
DO1–DO3
tPHL
50%
10%
tf
+3V
0V
tPLH
VOH
VOL
tr
Figure 2. Switching Characteristics
DRIVERS
3V
Tx1–Tx3
–3V
tSLH
3V
–3V
tSHL
SLEW RATE (SR) = – 3 V – (3 V) OR 3 V – ( – 3 V)
tSLH
tSHL
Figure 3. Slew–Rate Characterization
PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 1)
The most positive power supply pin, which is typically + 5
to +12V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to –12 V.
VCC
Digital Power Supply (Pin 16)
The digital supply pin, which is connected to the logic power sup-
ply (maximum +5.5 V). VCC must be less than or equal to VDD.
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal ground
pin of the EIA 232–E connector (Pin 7) as well as to the logic
power supply ground.
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232–E receive signal inputs whose volt-
ages can range from (VDD + 15 V) to (VSS – 15 V). A volt-
age between +3 and (VDD + 15 V) is decoded as a space and
causes the corresponding DO pin to swing to ground (0V); a
voltage between – 3 and (VDD – 15 V) is decoded as a mark
and causes the DO pin to swing up to VCC. The actual turn–on
input switch point is typically biased at 1.8 V above ground,
and includes 800mV of hysteresis for noise rejection. The
nominal input impedance is 5 kΩ. An open or grounded input
pin is interpreted as a mark, forcing the DO pin to VCC.
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing from
VCC to GND. A space on the Rx pin causes DO to produce a
logic 0; a mark produces a logic 1. Each output pin is capable
of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high–impedance digital input pins to the driv-
ers. TTL compatibility is accomplished by biasing the input
switchpoint at 1.4 V above GND. However, 5V CMOS compat-
ibility is maintained as well. Input voltage levels on these pins
must be between VCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA 232–E transmit signal output pins, which
swing toward VDD and VSS. A logic 1 at a DI input causes the
corresponding Tx output to swing toward VSS. A logic 0 caus-
es the output to swing toward VDD (the output voltages will be
slightly less than VDD or VSS depending upon the output
load). Output slew rates are limited to a maximum of 30 V per
µs. When the ML145406 is off (VDD = VSS = VCC= GND),
the minimum output impedance is 300 Ω.
Page 4 of 10
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