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M48Z02-70PC1_99 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z02-70PC1_99
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z02-70PC1_99 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48Z02, M48Z12
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
M48Z02 / M48Z12
-70
-150
-200
Unit
Min Max Min Max Min Max
tAVAV
Write Cycle Time
70
150
200
ns
tAVWL
Address Valid to Write Enable Low
0
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
0
ns
tWLWH
Write Enable Pulse Width
50
90
120
ns
tELEH
Chip Enable Low to Chip Enable High
55
90
120
ns
tWHAX
Write Enable High to Address Transition
0
10
10
ns
tEHAX
Chip Enable High to Address Transition
0
10
10
ns
tDVWH
Input Valid to Write Enable High
30
40
60
ns
tDVEH
Input Valid to Chip Enable High
30
40
60
ns
tWHDX
Write Enable High to Input Transition
5
5
5
ns
tEHDX
Chip Enable High to Input Transition
5
5
5
ns
tWLQZ
Write Enable Low to Output Hi-Z
25
50
60
ns
tAVWH
Address Valid to Write Enable High
60
120
140
ns
tAVEH
Address Valid to Chip Enable High
60
120
140
ns
tWHQX
Write Enable High to Output Transition
5
10
10
ns
WRITE MODE
The M48Z02/12 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
7/12
 

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