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74AC11SJX データシートの表示(PDF) - Fairchild Semiconductor

部品番号74AC11SJX Fairchild
Fairchild Semiconductor Fairchild
コンポーネント説明Triple 3-Input AND Gate
74AC11SJX Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
0.45
6.10
R0.09 min
12.00°TOP & BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
1.00
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
7
www.fairchildsemi.com
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