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630N Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталогеКомпоненты Описаниепроизводитель
630N N-Channel Power MOSFETs 200V, 9.3A, 0.30Ω Fairchild
Fairchild Semiconductor Fairchild
630N Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
SABER Electrical Model
REV May 2001
template IRF630N n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1e-12, rs = 7.75e-3, xti = 5.5, trs1 = 2.5e-3, trs2 = 2e-5, cjo = 8.5e-10, tt = 9.6e-6, m = 0.61)
dp..model dbreakmod = (rs = 4.2, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 1.15e-9, isl = 10e-30, nl=10, m = 0.86)
m..model mmedmod = (type=_n, vto = 3.25, kp = 5, isl = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.65, kp = 28, isl = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.8, kp = 0.05, isl = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.5, voff = -.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.5, voff = -7.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1) DPLCAP 5
c.ca n12 n8 = 1.6e-9
c.cb n15 n14 = 1.75e-9
10
RSLC1
LDRAIN
DRAIN
2
RLDRAIN
c.cin n6 n8 = 9.3e-8
51
RSLC2
dp.dbody n7 n5 = model=dbodymod
ISCL
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
-
50
DBREAK
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
LGATE
ESG
6
8
+
EVTEMP
RDRAIN
EVTHRES
16
+ 19 - 21
8
11
MWEAK
l.lgate n1 n9 = 5.12e-9
l.lsource n3 n7 = 4.24e-9
GATE
1
RGATE + 18 - 6
9
20 22
RLGATE
MMED
EBREAK
+
MSTRO
17
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
CIN
8
18
-
7
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
DBODY
LSOURCE
SOURCE
3
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = 2e-6
res.rdrain n50 n16 = 1.98e-5, tc1 = 1e-2, tc2 =3.7e-5
res.rgate n9 n20 = 1.61
S1A
12 13
8
S2A
14
15
13
RBREAK
17
18
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51.2
res.rlsource n3 n7 = 42.4
res.rslc1 n5 n51= 1e-6, tc1 = 4e-3, tc2 = -1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = -1.3e-5
res.rvthres n22 n8 = 1, tc1 = -3e-3, tc2 = 1.9e-6
S1B
S2B
CA
13
CB
+
+ 14
EGS
6
8
-
EDS
5
8
-
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 227
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*19))** 2.5))
}
}
©2002 Fairchild Semiconductor Corporation
Rev. B
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