NE1617A View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

NE1617A

Temperature monitor for microprocessor systems

NXP Semiconductors. 

NXP Semiconductors

NE1617A

Temperature monitor for microprocessor systems

Even though the NE1617A integrating A-to-D converter has a good noise performance,

using the average of 10 measurement cycles, high frequency noise filtering between D+

and D should be considered. An external capacitor of 2200 pF typical (but not higher

than 3300 pF) connected between D+ and D is recommended. Capacitance higher than

3300 pF will introduce measurement error due to the rise time of the switched current

source.

7.2 No calibration is required

As mentioned in Section 7.1, the NE1617A uses two well-controlled current sources of

10 : 1 ratio to measure the forward voltage of the diode (VBE). This technique eliminates

the diode saturation current (a heavily process and temperature dependent variable), and

results in the forward voltage being proportional to absolute temperature.

7.3 Address logic

The address pins of the NE1617A can be forced into one of three levels: LOW (GND),

HIGH (VDD), or ‘not connected’ (n.c.). Because the NE1617A samples and latches the

address pins at the starting of every conversion, it is suggested that those address pins

should be hard-wired to the logic applied, so that the logic is consistently existed at the

address pins. During the address sensing period, the device forces a current at each

address pin and compares the voltage developed across the external connection with the

predefined threshold voltage in order to define the logic level. If an external resistor is

used for the connection of the address, then its value should be less than 2 k to prevent

the error in logic detection from happening. Resistors of 1 k are recommended.

8. Temperature monitor with SMBus serial interface

8.1 Serial bus interface

The device can be connected to a standard 2-wire serial interface System Management

Bus (SMBus) as a slave device under the control of a master device, using two device

terminals SCLK and SDATA. The operation of the device to the bus is described with

details in the following sections.

8.2 Slave address

The device address is defined by the logical connections applied to the device pins ADD0

and ADD1. A list of selectable addresses are shown in Table 3. The device address can

be set to any one of those nine combinations and more than one device can reside on the

same bus without address conflict. Note that the state of the device address pins is

sampled and latched not only at power-up step, but also at starting point of every

conversion.

Table 3. Device slave address

n.c. = not connected

ADD0[1]

ADD1[1]

Address byte

GND

GND

0011 000

GND

n.c.

0011 001

GND

n.c.

VDD

GND

0011 010

0101 001

NE1617A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 20 March 2012

© NXP B.V. 2012. All rights reserved.

6 of 30

Share Link: