CMOS 64K (8K × 8) Static RAM
LH5164AZ8
DATA RETENTION CHARACTERISTICS (TA = -30 to +60°C)
PARAMETER
SYMBOL
CONDITIONS
Data retention supply voltage
Data retention supply current
VCCDR
ICCDR
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
VCCDR = 3.0 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
TA = 25°C
TA = 60°C
Chip disable to data retention
tCDR
Recovery time
tR
NOTES:
1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V.
2. tRC = Read cycle time
MIN.
2.0
0
tRC
MAX.
5.5
0.2
0.6
UNIT NOTE
V
1
µA
1
ns
ns
2
ADDRESS
CE1
tRC
tAA
tACE1
tLZ1
tACE2
tHZ1
CE2
tLZ2
tOE
tOLZ
tHZ2
OE
tOHZ
tOH
DOUT
NOTE: WE is "HIGH" level during the read cycle.
DATA VALID
Figure 3. Read Cycle
5164AZ8-3
5