STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
.
Table 11. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
PLS[2:0]=000 (rising edge)
2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge)
2 2.08 2.16 V
PLS[2:0]=001 (rising edge)
2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge)
2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge)
2.38 2.48 2.58 V
VPVD
Programmable voltage PLS[2:0]=011 (falling edge)
detector level selection PLS[2:0]=100 (rising edge)
2.28 2.38 2.48 V
2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge)
2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge)
2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge)
2.76 2.88 3
V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis
100
mV
VPOR/PDR
Power on/power down
reset threshold
Falling edge
Rising edge
1.8(1) 1.88 1.96 V
1.84 1.92 2.0 V
VPDRhyst(2) PDR hysteresis
tRSTTEMPO(2) Reset temporization
40
mV
1.5 2.5 4.5 ms
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
Doc ID 15081 Rev 7
39/98