STM32F100xC, STM32F100xD, STM32F100xE
Description
Figure 1. STM32F100xx value line block diagram
TRAC ECLK
TRACED[0:3]
as AF
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[3:0]
NBL[1:0]
NWAIT
NADV
as AF
80 AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
2 channels, 1 compl. channel
and BKIN as AF
1 channel, 1 compl. channel
and BKIN as AF
1 channel, 1 compl. channel
and BKIN as AF
4 channels, 3 compl. channels,
ETR and BKIN as AF
MOSI, MISO, SCK, NSS
as AF
RX, TX, CTS, RTS, CK
as AF
JTAG & SW
Cortex-M3 CPU
Fmax : 24 MHz
NVIC
GP DMA
12 channels
FSMC
EXT.I T
WKUP
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
TIM15
TIM16
TIM17
TIM1
SPI1
USART1
pbus
Ibus
Dbus
System
Trace
controller
Flash 512 KB
32 bit
VDD18
Power
Voltage reg.
3.3 V to 1.8 V
@VDD33
SRAM
32 KB
@VDDA
RC HS
RC LS
POR
Reset
Int
PLL
Supply
supervision
POR / PDR
PVD
@VDDA
@VDD
XTAL OSC
4-24 MHz
Reset &
clock
control
PCLK1
PCLK2
HCLK
FCLK
IWDG
Standby
interface
@VBAT
XTAL 32 kHz
RTC Backup
AWU register
Backup interface
AHB2
APB 2
AHB2
APB1
TIM2
TIM3
TIM4
TIM5
TIM12
TIM13
TIM14
USART2
USART3
UART4
UART5
16 ADC channels
(ADC_INx)
VREF+
VREF–
Temp sensor
12-bit ADC1 IF
@VDDA
WWDG
TIM6
TIM7
SPI2
SPI3
HDMI CEC
I2C1
I2C2
VDD= 2.0 V to 3.6 V
VSS
NRST
VDDA
VSSA
OSC_IN
OSC_OUT
VBAT = 1.8 V to 3.6 V
OSC32_IN
OSC32_OUT
TAM PER-RTC
(ALARM OUT)
4 channels
as AF
4 channels
as AF
4 channels
as AF
4 channels
2 channels
as AF
1 channel
as AF
1 channel
as AF
RX,TX, CTS, RTS,
CK as AF
RX,TX, CTS, RTS,
CK as AF
RX,TX, CTS, RTS,
CK as AF
RX,TX, CTS, R
CK as AF
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO,
SCK, NSS as AF
HDMI CEC as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
12-bit DAC1
IF
12-bit DAC2
@VDDA
DAC1_OUT as AF
DAC2 _OUT as AF
ai17515b
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C) or TA = –40 °C to +105 °C (junction temperature up to 125 °C).
Doc ID 15081 Rev 7
11/98